Electronic timing relay



May l1, 1954 H. H. ABELx-:w

ELECTRONIC TIMING RELAY 2 sheets-sheet '1 Filed 00T.. 3l, 1951 Hf HABELEW BY% 2 w ATTORNEY 2 Sheets--SheerI 2 Filed OCT.. 3l, 1951 FIG. 3.

C'ASCADED STAGES A /NTERLacK BETWEEN l2 AND /3, /5 AND o o o o o o O Ooo n o E o o o o o o u w E M 6 m, o o o so L rm E |||W| o o o w RM E o oo o o o Eo m M s u o o o o o o o o o o 44 77. E w r .n s r r r w Pra RD@w am mm MN mE wp w s 5E s E5 P RR m /A/D/C'AT'ES4 CONDUCT/N6 STATEIND/CA TES NON-CONDUCT/NG 5734 TE Patented May l1, 1954 UNITED STATESPAT OFFICE ELECTRONIC TIMING RELAY Harry Hugo Abelewjrooklyn, N. Y.,assignor to Mackay Radio and Telegraph Company, New York, N. Y., a'company of Delaware Application October 31, 1951, Serial No. 254,122

(Cl. Z50- 27) 11 Claims.

respectively, to a predetermined number of input pulses, and notnecessarily even numbers, and thereby establish a time ratio betweensaid output signals. y

A further object is to utilize the principles of interlock in cascadedbinary circuits in a manner f to permit flexibility of use thereof intiming devices.

Another object is to provide an improved timing circuit responsive to aplurality of uniformly timed input pulses of any frequency for theinitiation of plural output signals, having established therebetween apredetermined time relation.

Still another object of the invention is tozprovide vimprovedutilization of output signals' initiated by an electronic timing relayof the binary type.

Other objects and advantages are generally to improve and simplify ratiotype timer circuits for one or more of the objects above stated, andparticularlyrin respect to the establishment of a time ratio betweeninput pulse initiated output signals.

Other advantages and modications of the circuitry shown for explanatorypurposes will become readily apparent to persons skilled in the art uponexamination of the drawings, the speciiication, and the claims appendedthereto.

In the drawings, in which like parts are identied by the same referencenumerals,

Fig. l is a schematic diagram of an electronic timing relayincorporating` the principles of the present invention therein.

Fig. 2 illustrates in block a timing relay adapted to render a squarewave output pulse of four second duration with intervening spaces of onesecond.

Fig.Y 3 shows in chart form the inter-stage functioning of the device inresponse to a sequence of applied input pulses. c

Referring to Fig. 1, the apparatus includes generally, four individualmulti-vibrator circuits generically designated I0, II, I2 and I3 oi aknown type, and each including a double triode type of electron tube.The individual multivibrator circuits are of a conventional type, theoperation of which is too well known to warrant more than the briefexplanation below. For purposes of convenience of description, eachmultivibrator circuit will be referred to as including both right andleft hand sides which refers, of course, to the triode elements andassociated circuitry on each lside of the double triode tubes shown.VWhile the device is a ratio timer, and not simply an electroniccounter, it will be recognized that the circuitry resembles to someextent that of counters of the type disclosed in U. S. Patents 2,521,788to I. E. Grosdoff and 2,133,522 to J T. Potter; and in articles entitledNew vacuum tube scaling circuits of arbitrary integral or fractionalscaling ratio by Lifschutz, Physical Review, 1940; and A triode vacuumtube scale-of-two circuits by Lifschutz and Lawson, Review of ScientificInstruments, 1938, vol. 9, page 83.

A brief Vdescription of the operation of one of the multi-vibratorystages is included below as an aid to understanding the inventiveconcept, it being understood, as stated above, that each of the stagesoperates in a like manner in response to negative input pulses and thatno novelty per se resides in the circuitry of individual stages, butrather in the manner of interlocking stages for purposes above stated.Assuming that all stages are operating with the right sides of doubletriode tubes conducting, the bias on grid 2l ,stages I'I and I2 and alsoidentified by the letter Y. Since grid I1 obtains its bias through avoltage divider comprising resistors 24 Yand 43 from anode 2li, the biasthereof is relatively negative in respect to the potential of thecathode I9 to maintain the left side of the tube in al cutoff condition.

Assume that in the condition above stated, one of a sequence of.negative pulses, as vindicated at 26, from an oscillator-puiser orother It suitable source, not shown, is introduced through condenser 2'|to a mid-point between resistors 28 and 29 series connected betweenanodes I8 and 26 of tube I6. Pulse 26 instantaneously lowers thepotential of both anodes I8 and 2li, and both grids I'I' and 2|.Lowering the potential of grid I'I results in increasing the potentialof anode I8. Since the increase of anode potential is greater than thedecrease of grid potential, dueto amplification Iby the tube, thepotential of grid I'I does, in fact, undergo a net increase in positivepotential, due to direct coupling from anode 20 through the voltagedivider systems, resistors 24 and 43. A regenerative action, therefore,occurs with a drop in bias on grid 2| resulting in decreased conductionin the right half of the tube and consequent rise rof potential on anode2D, resulting from increased positive bias of grid Il, hence increasedconduction in the left half of the tube. The regenera- L tive actioncontinues until conduction terminates in the right half of the tube andbecomes maximum in the left half in a manner well known in the art. Anindicator lamp S is connected between anode 2B, in series with resistor3|, and ground 32 for the purpose of indicating a conductive conditionin the right side of the tube, lamp 3i) normally consisting of a neonbulb'.

As it is apparent, subsequent initiation of conduction in the right halfof the tube in response to a second input pulse results in a drop inanode potential, and in a step pulse, not shown, led throughdierentiating condenser 35 to result in negative peak pulse, indicatedat 3d, and fed to the second stage II in-the same manner that negativepulse 26 was fed to the first stage, and with the same eiect thereon.Each stage is coupled, as shown, to a subsequent stage to permit triggeraction therebetween in a manner which has heretofore been employed incascaded binary stages. Stages IG, II and I2 and the couplingtherebetween may be considered conventional, however, anode 31 of theright hand side of double triode tube 38 of stage I2, is coupled by lead40, through blocking condenser 4I and a voltage dividing networkcomprising resistors 42 and 43 to the grid Il of the first stage tubeI6.

The operation of the circuit so far described is as follows: Assuming aconductive condition in the right sides of all tubes prior to triggeringby input pulses, the iirst input pulse 26 triggers stage I to effectreversal of conduction, the right hand side now non-conducting, with aresultant rise of anode voltage, hence no negative output signal is fedtherefrom to stage II. The second input pulse again reverses stage I3and resulting conduction in the right side produces a pulse of a typewhich when diiferentiated by condenser 35 is of a negative peakedcharacter as shown at 34 to effect triggering of stage II from itsnormal state to a reversed state with the left hand side thenconducting. A third input pulse reverses conduction of stage ID with no:resulting negative output pulse of the type shown at 34, hence has noeffect on stage I I. The fourth input pulse again reverses conduction ofstageE Iii with a resultant reversal as above explained of stage I toreturn that stage to its initial state of conduction with a negativetriggering pulse fed to stage I2 for reversal thereof, With no change instage I3.

Heretofore, coupling between stage I2 and stage I through lead 40 had noeiect on the operation of the cascaded stages, but with the reversal ofconduction in stage I2 in response to the fourth applied input pulse,the potential of anode 31 of tube 38, raised upon termination ofconduction in the right side, transmits a step pulse over lead 40,dierentiated by condenser 4I to a positive peak pulse as indicated at49, to grid I`| of tube I5 for reversal of the conductive statepreviously established therein by the fourth input pulse. For reasonsstated above, stage II is not triggered in response to this reversal ofstage Iii. Stage I0 has, however, been returned to a condition to permita reversal thereof in response to a iifth pulse to produce a negativeoutput pulse for triggering of stage II, stage II being in a state ofconduction whereby the resultant triggering thereof does not produce anegative output pulse for triggering of stage I2. The sixth pulsereverses stage It with no resultant negative triggering pulse, being fedto stage II. The Various stages of the circuit are, however, now in acondition for simultaneous reversal, in response to the seventh inputpulse, of stages IG, II and I2, the reversal of stage I2 resulting,unlike the reversal of that stage in respense to the fourth pulse` in anegative rather than a positive output pulse 42, for initial triggeringof stage I3 from a state of right to left hand conduction.

The resultant step pulse from anode e6 ionizes neon lamp 53 allowingconduction through a Voltage divided network comprising resistors 52 and55, resistor 55 being connected to a source of negative potential, notshown, to maintain control grid tid of tube 46 at a proper negativepotential during periods of non-conduction of neon lamp t3, to maintaintube IIE in a gate closed position. However, the positive potentialapplied to grid 5G during periods of conduction of neon tube 53 inresponse to the rise of potential in the circuit of anode 5t is ofsuliicient value to overcome the bias of grid 54 thereby swinging tubeS6 to a gate open state. concurrently, with the opening of gate tube 4t,the positive pulse from anode 56 is returned through lead li! anddifferentiated by condenser 7|, and voltage divider network includingresistors 72 and i3, to grid I4 of tube '15, stage II, thereby reversingthe conductive state of stage II from right to a left hand conduction.While such reversal does not trigger'stage I2, the stages of the circuitare thereby arranged as to the relative conductive states thereof, toeiiect, in a manner described below, the closing of gate tube Q6 inresponse to a sequence of ve additional input pulses, namely the eighththrough twelfth total input pulses.

The operation of the circuit in response to the last five pulses is asfollows: The eighth pulse reverses the conductive state of stage It, asdo all input pulses, but does not trigger stage II. However, the ninthinput pulse triggers stages I, II and I2. Reversal of stage I2 by theninth input pulse functions in the manner as does the fourth input pulseto render stages It, Ii and I2 to the condition previously described. Itmust be remembered, however, that whereas stage I3 was in one of its twobi-stable states upon application of the fourth pulse, it has beenpreviously triggered by the seventh input pulse, to the oppositebi-stable condition, but since no stage is triggerable by positive inputpulses, as distinguished from positive peak pulses fed by the interlocksdirectly to the grids of the tubes, the positive step Wave output fromstage I2 in response to the ninth input pulse does not changetlie'sftate foiy :stage `l3. The ninth pulse returns `stages l0, lil andl-2 to :the same relative conditierras A`did the fourth pulse', hencethe vten-th and 'eleventh pulses "effect these stages exactly as did theiifthand sixth pulses 'above described. llpplicatio'n of the twelfthpulse results, in a manner described in connection with the effect oithe seventh pulse, in 'triggering fall Ystages lll, "lll, l2 and vI-l,but since Ystage I3 is now in a state 'of'left hand -condu'ction theresulting triggering pulse from stage i2 reverses stage l-3 for estab-4Icislfiment "offcondution "in the rig-ht side, with 'a :resultingnegative step -output which extinguishes 'neon `lampi`53 :and lpermitsthe negative bias vfrom source -EG3- to 4swing grid '54 to cut-off 'and'clos'egate tube '46.

The net of the `ol'oera'tion above described that interlock lead 4D istwice employed during fa sequence of twelve pulses -to reverse, Vinresponse to a positive output pulse from stage I2, the con duc'tii'leJstate of stage lll as established 'by 'the ,input pulse which'initiated the reversing output pulse, namely the four-th and ninthinput pulses. Interlock lead T0 was employed once, subsequent tothe.iirstzreversal of stage I0 through lead 40, in `response to the fourthinput pulse and 'prior to the second reversal of stage 'I' in responseto Ithe 4ninth input pulse, for v'reversal of stage Il vby the seventhinput pulse. rIhe eiiect of the two interlocks fis such that the circuitfunctions, when Iactuated by input pulses of equally timed intervals, toproduce Sa `first pulse 'in known time delayed relation to a time basecomprising 'the nrst applied input pulse and a second pulse at axed timeinterval therefrom. These two pulses comprise a timed duty cycle inrespect to a time base.

As shown at V80, a reset pulse, indicated at 8|, maybe applied to thesystem for the .purpose Aof resetting the four stages to the initialstate rof right yhand conduction, it being obvious that the positivereset pulse when applied drives all right -gridsof the'double tubespositive to intiate conduction in the fright sides, to be 'maintaineduntilapplication of input pulses in the vmanner above described. Tube 46is illustrated in Fig. .1

as being yof `the double Ycontrol grid type com monly employed in gatingcircuits, the vlower control grid 86 functioning as a signal input gridmaintained at a proper negative 'potential from -a source. indicated atEGA. Positive input pulses vmay be applied through condenser -90 toeffect negati-Ve peaked output pulses from capac- `itor 92 when theytube is in a gate open condition, diiring periods as above describedwith vgrid -54 maintained below cut-ofi. With grid 54 Lbiassed belowcut-off, input pulses applied to capacitor 90 does not cause tube 46 toconduct Aand consequently does not result iin any output pulses atcapacitor 92.

The device above described, unlike conventional decade counters, ndsmany uses as an interval timer, and particularly as an interval timerYadapted to -dene a time interval which starts in time delayed relationto an actuating pulseand `termina-tes at a predetermined timethereafter.-

lAs shown in Fig. l, the -flrst or input stage I0 vof the circuit shownmay be fed by a sequence of --actuating pulses indicated at 26, :as forexamplafrom :an loscillator-pulser "of 1a type delivering en output of:repetitive pulses 'accurately spaced respect Lto a time intervaltherebetween. fAs will befsiiown, the multipleuses for which' theses/icev-is adapted contemplates Aa predetermined correlation between the totalnumber of cascaded stages, the interlocking ar'- rangement between thedifferent stages, and the magnitude of the time interval between theactuating pulses fed to the circuit. Oscillatorpulsers as well as.pulsers of other types are well known in the art, hence will not bedescribed.. It will be understood, however, that while the timer isoperative vin response to a sequence of input pulses and, therefore, ina sense, 'the circuit maybe considered as counting a number of inputpulses, the function of the circuit is not simply to deliver an outputpulse representative of the arithmetic sum of a plurality oi inputpulses, a result which is obtained by scale-down counters, but rather isto produce a signal, representative of a time interval as `measuredbyplural input pulses, after receipt of an initial actuatingV input pulsewith a. second output signal lat a predetermined measured interval -inrespect to the first signal,

For example, the device is particularly adapted to perform, amongothers, the following functions:

(l) `To automatically indicate two successive time intervals, t1 and t2,provided the ratio tizia is a rational number; i. e.

t1 IL where n and m are positive integers.

(2) To 'automatically 'time an interval tz-ti, provided t2 t1 is arational number.

(3) To provide square-wave excitation of van electronic orelectro-'mechanical actuator such as a gate or relay with rthe edges ofa 'square- Wave indicative of a time ratio or duty cycle, provided theduty cycle can be represented as a rational number.

The selection of stage-pairs to be interlocked, `in respect to thefrequency of the voscillator-- pulser to be employed is determined forveach specific application within the capability of the device, by thealgorisrn described below.

While not shown in Fig. 1, the above described interlocking couplingsmay be controlled, through multi-position switches to be switched 'atvwill between various stages to provide a convenient means for changingvthe time interval ratio, or duty cycle of the vIdevice for universaluse in association with a sequence of actuating pulses of various timeintervals therebetween as desired, for example, in the laboratory. Theparameters to be determined for each application of the device are theoscillator frequency f; the number of interlocking connections n; andthe pairs of stages interlocked by each connection Puk. These,parameters are specified by the algorismas shown by the followingexamples.

Example 1.-Required to energize a relay coil cyclically, with the coilenergized .for four consecutive seconds and de-energized Aduring lthefifth second.

Procedura-4a) The ratio of the two intervals is ifi Since thegreatest-common factor of 44 and 1 is l, this specifies the frequency ofthe oscillator- .pulser as l cps.

(lo) 'Since 4:22, three -cascaded stages are requ-ire'dforthe rstinterval.

` Y (c.) To specify interlocking paths for the second interval, performbinary subtraction of This species interlock coupling Pai and Paz. Sucha relay, as illustrated in Fig. 2, a three stage relay, with interlocksbetween both the third and second and third and first stages isproductive of a square wave output pulse of four second duration withone second spaces. Such a device may be utilized as an automatic keyerfor automatic intern-ational alarm type transmission equipment.

A three stage relay, with interlocks as above described is illustratedin block diagram, Fig. 3.

The inventive concept above taught has also been advantageously employedin timing relays 4in automatic alarm systems of the type shown anddescribed in my copending application entitled Signal Selector DeviceSerial No. 254,121 filed simultaneously herewith. The problem presentedin respect to the timing relays employed therein included, for example,the provision of a timing device to deliver an output gate opening pulse31/2 seconds after initiation of relay operation by a received signaldash, and deliver a gate closing pulse exactly 21/2 seconds thereafter.The problem and the solution thereof are shown below as Example 2.

Example 2.-Required to open a gate 3.5 seconds after an arbitrary timetaken as zero, to maintain the gate open during the 2.5 seconds afteropening and then close it.

Procedura-To set up the device for successive intervals of 3.5 and 2.5seconds.

anni

The greatest common factor of t1 and t2 is 1/2. This specifies theoscillator-pulser frequence as 2 cps.

(b) Since 22 7 23, four cascaded stages are required and the outputsignal is obtained from the fourth stage.

(c) Perform binary subtraction This specifies Pa,1 as an interlock.

(d) Perform binary subtraction 7-5 or 1110 1o This species 134,2 asanother interlock. Thus the number of stages are chosen, and theinterlocks are connected as in the Fig. 1 embodiment of the inventionabove described.

The circuit of Fig. 1, above described in detail, -when actuated by asource of pulses spaced at one-half second intervals is productive ofthe results desired in Example 2 above.

What is claimed is:

1. In an electronic timing relay device adapted for actuation by asequence of timing pulses to produce square wave output signalsindicative of a measured time delayed interval following initiation ofsaid device, the combination with a group of stages, each stagecomprising a bi-stable circuit adapted to be triggered from one to theother of two stable conditions by an input pulse, and circuit meansconnecting said stages in cascade for transmission of output triggeringpulses from one to the other of said stages for binary counter actiontherebetween; of circuit means interlocking one of said stages to anon-contiguous preceding stage for reversal of the stable condition ofsaid preceding stage in response to an ouput signal from said oneinterlocked stage, and circuit means interlocking the last one of saidstages to another non-contiguous preceding stage for reversal, inresponse to an output signal from said last stage of the stablecondition of the previous stage interlocked therewith, and meansassociated with the rst mentioned of said interlocked stages to effectthe rise of a square wave pulse in response to an output signal fromsaid first mentioned interlocked stage, and to effect the fall of asquare Wave pulse in response to an output signal from said last stage.

2. In a timing device, a group of stages, each comprising a triggercircuit having two stable conditions between which the circuitalternates in response to introduced electrical impulses, meansconnecting said stages in series for normal operation in the binary basenotation and including means whereby each stage except the highest inseries, on changing one of its stable conditions in response to animpulse transmits an operating impulse to the next highest stage in theseries, means for applying operating impulses to the lower stage in theseries, means including a circuit interconnecting a higher stage in theseries to a non-contiguous lower stage for effecting, only uponoccurrence of a change in the higher stage, from one to the other stablecondition, a reversal of normal binary operation of said lower stage andpermitting the normal binary operation during the other stable conditionto thereby convert operation from the normal binary to another basenotation, and a second circuit interconnecting another higher stage inthe series to another non-contiguous lower stage for preventing, onlyupon occurrence of a change from one chosen stable condition, a normalbinary operation of said lower stage while permitting a like operationduring the other stable condition for conversion of operation from thenormal binary state to another base notation.

3. In an electronic timing relay, a source of timing pulses, a group ofstages each comprising a trigger circuit having two stable conditionsbetween which it alternates in response to electrical impulses, meansseries connecting said stages for transmission therebetween, upon changeof a lower stage from one to the other of its stable conditions, animpulse to the contiguous higher stage, means for introducing saidtiming pulses to the lower stage in the series, means connecting thehigher stage in the series to a non-contiguous lower stage in the seriesfor reversal of condition of said lower stage in response to an outputimpulse from said higher stage, and' means connecting a stageintermediate said first mentioned interconnected stages to a lower stagefor transmission of output signals from said intermediate stageresulting from the triggering thereof from one to the other of itsstable conditions back to said lower stage for reversal thereof from oneto the other of its stable conditions.

4. An interval timer having in combination a plurality of bi-stablecircuits cascade coupled for transmission of actuating pulsestherebetween, means associated with the iirst of said cascade coupledcircuits for repetitive actuation thereof between its bi-stable statesby a sequence of pulses spaced at equal time intervals. circuit controlmeans associated with the last of said bi-stable circuits and adapted tobe actuated between two circuit controlling states in response to outputpulses from said last bi-stable circuit resulting from a change from oneto the other of its bi-stable states, and means interlocking one of saidbi-stable circuits other than the rst or last of said circuits with therst of said circuits for reversal of the input pulse initiated stablecondition of said first circuit in response t0 an output pulse resultingfrom a change of state of said bi-stable circuit interlocked therewith.

5. The device of claim 4 including interlocking means between said lastbi-stable circuit and a preceeding circuit disposed intermediate saidrst mentioned interlocking circuits whereby said last mentioned circuitis reversed in respect to the stable condition thereof in response to anoutput pulse initiated by said last circuit in response to a change ofstate of said last circuit.

6. An electronic timing device having in combination means forinitiation of evenly spaced timing pulses, a sequence of three stageseach comprising circuits having three stable conditions, means cascadeconnecting said stages for binary action therebetween, means connectingsaid pulse initiating means to the iirst stage of said sequence foractuation from one to the other stable condition in response to eachinput pulse, means interlocking the third last stage of said sequence tosaid rst stage for reversal of the stable condition of said first stagein response to a reversal of said third stage from one to the other ofits Stable conditions, and means interlocking said third stage with thesecond stage of said sequence for reversal of condition of said secondstage in response to a change of said third stage to the other of itsstable conditions.

7. The device of claim 6 including a gating circuit adapted to be swungto a gate-open position in response to an output signal from said laststage initiated by the rst change thereof from one to the other of itsstable conditions and to be swung to a gate-closed position in responseto the output signal from said third stage resulting from the returnthereof to the other stable condition.

8. An interval timer including four stages each comprising a bi-stablecircuit, means cascade connecting the rst three of said stages fornormal binary operation of said third stage in response to a sequence offour input pulses introduced to the first of said stages, meansinterlocking the third stage to said rst stage for reversal of thebi-stable condition thereof as established by said fourth applied inputpulse in response to an output pulse from said third stage initiated bya reversal of the bi-stable condition thereof by a fourth input pulse,means connecting said third and fourth stages for binary actiontherebetween in response to a subsequent output pulse from said thirdstage resulting from a return thereof to the bi-stable conditioninitiated prior to reversal thereof by said fourth pulse, and meansinterlocking said fourth and second stages for reversal of the bi-stablecondition of said second stage in response to a seventh input pulseapplied to said first stage.

9. The device of claim 7 including circuit control means operablebetween open and closed positions, means connecting said circuit controlmeans to said fourth stage for actuation thereof to one circuitcontrolling position in response to an output pulse from said fourthstage responsive to the seventh applied input pulse, and for actuationto the other circuit controlling position by an output pulse from saidfourth stage responsive to the twelfth applied input pulse.

10. In an electronic timing device adapted for actuation by a sequenceof timing pulses to produce output signals indicative of a measuredinterval, time delayed in respect to initiation of said device by thefirst of said timing pulses, the combination with a group of stages,each stage comprising a bi-stable circuit adapted to be triggered fromone to the other of two stable conditions by an input pulse, and circuitmeans connecting said stages in cascade for transmission of outputtriggering pulses from one to the other of said stages for binary actiontherebetween; of circuit means interlocking one of said stages to apreceding stage for reversal of the stable condition of said precedingstage in response to an output signal from said one interlocked stage,circuit means interlocking another of said stages to a preceding stagefor reversal, in response to an output signal from said otherinterlocked stage of the stable condition of the stage interlockedtherewith, means associated with the first mentioned of said interlockedstages and responsive to the actuation thereof for initiation of a firstoutput signal, and means associated with said second mentionedinterlocked stage and responsive to actuation thereof for initiation ofa second output signal.

1l. An interval timer including a sequence of three stages eachcomprising a bi-stable circuit, means cascade connecting said stages forbinary action therebetween, means for the initiation of evenly timedinput pulses, means connecting said input pulse means to the first stageof said sequence for actuation thereof` by input pulses, circuit controlmeans operable between two circuit controlling positions, meansconnecting the third stage of said sequence to said circuit controllingmeans for actuation thereof to one circuit controlling position inresponse to an output pulse resulting from the switching of said thirdstage from one to the other bi-stable state, and to the other circuitcontrolling position in response to switching of said third stage to theother bistable state, means interlocking said third stage to said rststage for reversal of said first stage in response to a reversal of saidthird stage, and additional interlocking means connecting said thirdstage to said second stage.

References Cited in the file of this patent UNITED STATES PATENTS NumberName Date 2,306,386 Hollywood Dec. 29, 1942 2,410,156 Flory Oct. 29,1946 2,536,035 Cleeton Jan. 2, 1951 2,538,122 Potter Jan. 16, 1951 OTHERREFERENCES Electronic Counters, by Grosdoff, pages 437-447 of RCAReview, September 1946, vol. VII, No. 3.

Predetermined Counter for Process Control, by Blume, from February 1948Electronics, pages 88 to 93.

